1364.1-2002 IEEE Standard for Verilog Register Transfer - download pdf or read online
Regular syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this general.
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Extra resources for 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis
It is an error if the attribute is applied to an asynchronous set or reset signal. NOTE—Deﬁnitions: Set logic—the logic that sets the output of storage device to 1; reset logic—the logic that sets the output of storage device to 0. When no signal names are present, both set and reset logic signals shall be applied directly to the set/reset terminals of an edge-sensitive storage device. When signal names are present, only the speciﬁed signals shall be connected to the set/reset terminals (others are connected through the data input of the edge-sensitive storage device).
Assign qbar = ~q; // Equation for test point. always @(posedge clk or posedge rst) 26 Copyright © 2002 IEEE. All rights reserved. PROBE_PORT (1)) ff #(WIDTH_ONE, PROBE_PORT_ON) // Bring probe port out. PROBE_PORT (0)) ff #(WIDTH_ONE, PROBE_PORT_OFF) // Do NOT bring probe port out. rst (rst)); endmodule // top NOTES 1—This attribute is needed for the veriﬁcation of gate-level model designs at the “grey-box” level where internal signals may be needed for triggering of events in a veriﬁer (example, the occurrence of a simulation push/pop of a ﬁfo).
36 Copyright © 2002 IEEE. All rights reserved. 6 regs Supported. See Clause 5 on how edge-sensitive and level-sensitive storage devices are inferred. 1 Operators and real numbers Not supported. 2 Conversion Not supported. 9 Arrays Supported. 1 Net arrays Supported. 2 reg and variable arrays Supported. 3 Memories Supported. Copyright © 2002 IEEE. All rights reserved. 2 Local parameters—localparam Supported. 11 Name spaces Supported. 38 Copyright © 2002 IEEE. All rights reserved. 1 Operators Supported.
1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis